Just want to give Bobby a huge thank you for your assist in diagnosing my LG issue as a Z Sus board.  I put TV back together last night and did a test run before putting the back panel on.  Sure is a great feeling when that "No Signal" comes right up, flipping inputs to Ant. channel 4-1 brought the full 720p of plasma beauty.
All other blog sight troubleshooting was leading to Y Sus and/or Y Buffer, however my symptoms where a little different.  The sound was still good and screen was "nearly" all black.  About 10% of screen was blotchy but still visible.  That alone was a huge difference from all problems I saw out there on the web.  I recommend Coppell TVRepair, as I got a good warranty period on the replacement board, and respect these guy's hard-core professionalism and high expectation for attention to detail.  

I've got an LG42PC3D with no screen (probably no sound).
Taking up a lot of floor space needed for other work.

It had bulging caps on the PSU 5V rails, that were replaced.

All supply rails seem normal, except for -VY on Ysus board.

Ysus drive output has no negative going ramp portion.
Positiive-going ramp is visible.
Zsus is synced and functional.

PS101 was pulled and tested it separately - it produces the
expected regulated -200V, loaded at 8W (5KR).

In circuit, it's overloaded and pulled to within 30V of chassis
ground.

What are the likely paths for overload of this rail? 900V mosfets
seem to be functional, though all are hot.

Adjustment component strings for setup and setdn seem normal.

No schematic for this circuitry here, but could troubleshoot at
the component level, if one were available. Have done a lot of
work on SMPS and power interface over the years.

There are LG training manuals for similar (later) models - closest
probably LG42PC5DC, with a PFC input, but very few good
circuit references that apply to their earlier versions of Ysus.

Damon Morrow's 'Plasma TV Repair' is instructive but only
offers drawings suggesting the location of supply voltages
and their controls, without ground references or IPC/external
circuit differentiation.

I accidentally applied power, once, with Y buffer board not
connected (socket mis-registration). Under those circumstances,
the -VY still did not rise on it's 220KR bleeder.
Wouldn't make this kind of test intentionally, as am unfamiliar with
potential damage that might result.

With a schematic. I could probably solve the issue fairly quickly.

there's an SMD electrolytic capacitor near optocoupler to the right of the heat sink with the output switching mosfets.
Replace it.

If that doesn't help replace the first transistor on that heat sink...or the seccond, whichever one is in the -Vy circuit.
I think it was 9NK70Z, but I may be wrong.

This is off the top of my head several years old knowledge.

Using the training manual for 42PC5DC, I marked
up the supplies and big switch functions in the 42PC3D.

http://ve3ute.ca/query/42PC3D_Panel_Drive.jpg

Both -VY(setdown) and Vsc(setup) are solid, and there
are no flakey filter components on their outputs.

All of the heatsunk mosfets have their own gate drive
power developed by IC101 driving small transformer
T101. The gates are driven by digital optocouplers
with 600mA push-pull outputs.

I'm seeing what looks like heavy loading of the gate
drive circuit supply rails for the two HV fets. This
loading isn't present when the isolated multi-output
converter around IC101 is powered alone from P1, on
the board, out of the box.

It's possible that the gate of the setup fet is not fully
involved under these conditions, as it's supply seems
to depend on a sort of bootstrap situation - It's gate power
being diode isolated, the fet source having no direct
connection to this supply - the parallel fets have to turn on
before the '2nd 900v fet' gate drive gets a supply voltage
refreshed.

The two 900V fets (setup +setdn with no visible board
ident)) were replaced earlier, just because it was
quicker than thinking about it too much.

It looks like the -VY circuitry can only be overloaded
through the three parallel fets. So far I see nothing
in these three fets, or their in gate drive circuit that would
be responsible.

I found a picture of the 6871QYH053B used here.
Not much definition, but might jog memory.

http://ve3ute.ca/query/6871QYH053B_2.jpg

It turns out that power for gate drive of both the 2nd 900V mosfet
(ramp up) and the top 3 parallel mosfets (pass) are results of
bootstrapping.

This may give the illusion of supply irregularity, if the signals to
the Y-Sus panel are intermittent. The ramp-up supply gets a chance
to refresh during the pre-ramp chatter, when its source is pulled
to ground by the IPM, but the parallel section's gate supply seems
to be refreshed only when pulled down to -VY, which is a bit of a puzzle.

Time to see if the switch functions follow their optocouplers' input signals
correctly.

The gate drive to 2nd 900V fet (s-up) is as expected.
There is no gate signal or gate enhancement on 1st 900V
fet (s-dn), during the active drive period, so no negative
drive would be possible, where expected, even if -VY was
of normal unloaded amplitude. This ist 900V fet gate is
turned on intentionally outside of the active drive period,
however - something not expected for a typical Y-SUS  
output.

The three parallel pass fets receive gate signals and gate
enhancement for the entire active period, (off outside of
that time) which doesn't make much sense if a negative
Y-SUS signal is to be developed from -VY. The pass fets
would look like a short, through D14.

Without any gate drive to the 1st 900V fet in the active period,
its gate signals look to be a simple inversion of those presented
to the 3 parallel pass fets.

It's possible that something is sensing the -VY low value under
overload and inhibiting its gate signal, but only during the
active period (?).

Anyways, gate drive seems secure for the three switches.

I hope that the slope of the ramp-up/ramp-dn waveform
isn't simply expected to be controlled by the 4n7 and 2n2
capacitor networks connected from drain to gate of the 900V
parts . . . . . .

From the training manual for 50PC1DR, which has approximately the same manufacturing date, I see waveforms for Ysus that start and end with -VY. This justifies gate drive to the lower 900V fet, outside of the scan sequence.

Now if I can just figure out why there's no gate pulse during the VSETdn time, the logic issue could be resolved.

My observations on the gate drive to the parallel fets still goes - they would have to be off, within the scan
period at any time that the 1st 900V fet was turned on, in order to allow a negative output. If the gate
control to produce the VSETdn ever shows up, it might be an issue. At the moment they turn off outside
of the scan period, so an output settling at -VY shouldn't be a problem.

Still haven't found a source for overload of the -VY rail.

RL

I located the 'short' that was overloading -VY.

One of the parallel fets was avalanching early - (though it measured out OK).
Eventually went low-Z between drain and gate.

After replacing all 3 with working subs (rdson=80mR vs 40mR req - good subs are on order)
the -VY is back and the Ysus output follows any requested -excursion. As with old 50in version,
this Ysus output stays negative between panel drive periods.

There is still no set-down ramp, or a gate drive signal, at the correct time, to create one.

Another thing I haven't mentioned previously, because it wasn't obviously odd to me,
is that the panel drive waveform has two set-up ramps in the drive period.

I simply expected to see two set-down periods, when function could be restored.
From examination of typical waveforms, this is apparently not normal - a panel
drive pattern may start with hash, but will include only a single set-up ramp followed
by a single set-down ramp.

It looks like the controller providing the gate signals isn't operating as expected, to
drive the panel as expected.

Anything I can do, short of restoring firmware (not likely possible), or replacing the
controller board whole?

Is there a firmware reset-to-factory procedure that is not published? Reprogramming
seems to require a special harness and PC program (from XP era?)

Anyone?

RL

It looks like this model doesn't expect a return to zero after the set-down
ramp completes. This part of the waveform - its end - does have a ramp,
so 'set-down' could conceivably be functional.

Perhaps the issue is with the double set-up waveform, alone?

On second sight, it looks like the actual Ysus output waveform could be
normal.

The double set-up ramp is visible on the buffer test point, alone.

I'll have to do some better syncing on the waveforms in these
two places before I can get a better idea of what's going on.

RL

The buffer isn't pulling low.

As a result (-200V) -Vy increases towards -250, even if the -VY bleeder is reduced to 20K.

I think the buffer board might have been used in other models - so a more available spare?

RL

With the Y buffer board replaced, things are not much better.
-VY is no longer drawn to exceed it's -200V regulated value.

The Ysus waveform into the buffer is still either a double or single
sus_up, with no negative going sus_dn, unless the normal return
to -VY (outside of drive signal period) is enforced per earlier
50PC1 models.

A double sus_up waveform into the buffer is presented on the buffer
test point as the sus_up with peak voltages stored until the drive signal
period ends. Then it slowly returns to zero

http://ve3ute.ca/query/42PC3D_Y_SUS_issue_211005a.jpg

42PC5DC typical Y_SUS-
http://ve3ute.ca/query/42PC5DC_Y_SUS_waveform.jpg

50PC1DR typical Y_SUS
http://ve3ute.ca/query/50PC1DR_Y_SUS_waveform.jpg

Adjustment of the variable resistors in the miller circuit
of the 900V mosfets has no visible effect on gross levels
or dv/dt in the recorded Y_SUS waveform.

RL

I suppose that if the SUS_UP slope was slower and continuous,
then a ~ book waveform could be created, using the end of
drive period as the SUS-DN, per older 'return to -VY' methods.

The book timing (40us/div) suggests that SUS-UP and SUS_DN are
expected to complete in ~ (+)100us (-)80us time periods.

http://ve3ute.ca/query/42PC5DC_Y_SUS_waveform.jpg
http://ve3ute.ca/query/50PC1DR_Y_SUS_waveform.jpg

Sick puppy's SUS_UP (50us/div) is too quick.

http://ve3ute.ca/query/42PC3D_Y_SUS_issue_211005a.jpg

The components in the 900V part's set-up miller network seem
to be OK individually. Maybe if it was slower, the waveform might
magically turn into a single pulse, rather than a double one. . . . . ?

Still don't know why the buffer test point doesn't follow SUS_OUT.

I'm working with a dark screen - a few pin-pricks of color
visible in a dark room.

RL

I see adjustment on set-up - it never reaches Vs (+185V on this model) at
any ramp setting. There is no effect on the timing of the fast turn-off
drive occurring between the two set-up ramp pulses. As a result, slowing
the ramp simply reduces the peak amplitudes being reached before the
'mistimed' turn-off occurs.

It indicates that the mis-timed turn-off is not the result of set-up peak
amplitude, if there is some kind of monitoring circuit somewhere, producing it.

The buffer board chips are getting hot, fast, so I don't run it for very long.

Occasionally, I can see the buffer test point voltage go below ground during
intervals between drive waveform periods, but never anywhere near -VY, where
set-down parks the YSUS drive to the buffers during the same interval.

RL

Will probably be replacing the controller board, in an attempt
to get useful gate drive signal timing. Where I am, this
generally means another $50 and a week's delay.(for a $13 part).

It blocks an isle, for any test procedure, and can't be safely
stored in a disassembled condition.

RL

A replacement control board produced normal Y_SUS output waveforms
and some screen activity. The buffer test point, however still does not
follow Y_SUS, to go negative during set-down. or in between drive
periods. When set-down completes, the buffer test point floats negative
to ~ -35V in between drive periods, vs the -200V on -VY and Y_SUS.

Something on the buffer board, near the top, sparked on first power-up
with new control board installed - but all 22R limiters in that area remain
intact, so it wasn't one of those going open.

Only the very top row of buffers now produce screen artifacts, so it looks
like the buffer board needs replacing, again.

Set-up and Set-dn adjustments can wait till the full screen is illuminated
in all sectors.

RL

The spark on the buffer board (at first turn-on with new controller)
was from R15, a 47R 1W smd resistor in parallel with D13.

Why would this pop NOW, when the only difference was waveform
integrity? The same peak voltages were previously applied when
the drive info was corrupted.

Are overheating buffers a symptom of something else? The load is the
(capacitive) panel - which, from all observations, is capable of illumination.

RL

If the 47R resistor is simply a part of an RCD snubber, then it could only
likely fail due to series cap shorting, but I don't measure a cap short.

I'll replace the cap and the resistor anyways and see what happens.

How a snubber failure could knock out basic function, elsewhere, is another
question. No similar buffers appear in the better-documented models being
used as reference.

RL

Well, how or why don't seem to figure.

Replacing the resistor and cap allowed full screen appearance,
though it was far from a steady white screen.

A vertical yellow/red/white section was jumping from one place to
another (left/right/center) at random - until the same resistor popped
again, leaving the single horizontal section across the top.

Can't blame the cap this time, and that RCD network must be doing
a hell of a lot more than just snubbing a switching node.

umm . . .

RL

FYI - I ran across Y_SUS waveforms in the product training manual
for 50PC1DR that included a double setup pattern and a single set-up
pattern within the trace illustration.

Elsewhere, a double setup pattern is illustrated as being characteristic
of a dual-scan system.

Nothing like this in docs for 42PC variants.

RL

Should probably mention that Y_SUS waveforms are supposed
to be calibrated with a white screen image signal. I haven't
been providing any input signal during this work, but then I
haven't been 'calibrating' anything yet.

If a non-white screen image could produce any of the symptoms
or damage previously mentioned, I would be oblivious, unless
reassured by someone else who knows. Nothing in the literature
I've read so far suggests possibility of damage due to lack of a
signal input.

hm . . . 74AC540SJ (SOP body) is no longer manufactured and
SOIC body size is too big to fit footprint. Why would you discontinue
a smaller body size (that might be kluged onto the bigger footprint) ?

RL

Have had advice to check screen for possible burnt
pixels. Their presence turns plasma screens into scrap,
but no hint as to actual performance in presence of a
burnt pixel.

Also, a service advisory was issued to include this model,
that might rightly produce a chuckle:

(no date)

2006 LCD, PDP, & MDPs that use the ARM CPU & Micronix Flash Memory.

Symptom:

During a specific date range the customer may turn on the TV and there will be no video
or audio. The problem will first occur: Jun 20th, 2006, 14:03 ~ Jun 21st, 08:14. Then
it repeats every 194 days.

Solution:

Temporary fix is a hard reset (unplug for a few seconds). New firmware is available as
a permanent fix. The update needs to be done by a service center.

Models:

32LC2D, 37LC2D, 42LC2D, 42PC3DV, 42PC3DVA, 42PC3D, 50PC3D, 50PX2D, 50PX2DC.

Tools Required:

Computer
Null Modem Serial Cable

Tools Supplied:

Instructions
Firmware Files
DTVLab Update Software

Versions:

32LC2D-UD : Ver3.06.1
37LC2D-UD : Ver3.06.1
42LC2D-UD : Ver3.05.1
42PC3DV-UD(42PC3DVA-UD) : Ver3.06.1
42PC3D-UD : Ver3.07.1
50PC3D-UD : Ver3.07.1
50PX2D-UD(50PX2DC-UD) : Ver3.10.1
42PC3DV-UD,42PC3DVA-UD : the same as S/W
50PX2D-UD,50PX2DC-UD : the same as S/W

You'd figure that such an event might produce a
surplus of materials for use in re-flashing these
things; . . . .but . . . nada.

RL